The present invention relates to a frequency synthesizer using a phase locked loop (PLL) and, more particularly, to a PLL synthesizer capable of switching the output frequency thereof at high speed.
A conventional PLL synthesizer has a reference frequency oscillator, a fixed frequency divider for dividing the output frequency of the oscillator, a voltage controlled oscillator (VCO), a variable frequency divider for dividing the output frequency of the VCO, a phase/frequency comparator for comparing the outputs of the fixed and variable frequency dividers to output a difference therebetween, a charge pump to which the difference or deviation is applied, and a loop filter receiving and smoothing the output of the charge pump and feeding back the output thereof to the VCO as a control voltage. It is a common practice with this type of PLL synthesizer to cause the loop filter to select either one of a greater and a smaller time constant in order to enhance high-speed frequency switching and to stabilize the frequency. More specifically, the time constant of the loop filter is reduced at the time of frequency switching so as to promote rapid tuning. After the frequency switching, a lock signal is fed from the phase/frequency comparator to the loop filter to increase the time constant of the filter, thereby stabilizing the frequency. In practice, however, at the time when the switching operation is completed, the control voltage applied to the VCO has been deviated from an expected value due to the delay particular to detection and switching. Therefore, the initial frequency just after the switching is different from a predetermined one with the result that the switchover of the time constant of the loop filter is delayed. This in turn delays the tuning time of the PLL and prevents the frequency to be switched over at high speed.